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Senior Design Engineer

155790
San Jose, CA, United States
Aug 20, 2018

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Job Description

Description

Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today's most advanced electronics. Among the broad range of end markets we serve are:

  • Aerospace/Defense
  • Automotive
  • Broadcast
  • Consumer
  • High Performance Computing
  • Industrial / Scientific / Medical (ISM)
  • Wired
  • Wireless

 

Define, design, verify, and document ASIC development. Determine architecture design, logic design, and system simulation. Work in a state-of-the-art verification environment using UVM verification methodology and C. Own block level test bench and work on full-chip, system level verification, silicon bring up and silicon validation. Create block level verification plan, test plans and full chip test plan. Develop block level test bench and tests in UVM methodology including scoreboard. Work on subsystem level verification. Work with designers to get the coverage closure. Port the block level tests to full chip test bench. Integrate VIPs as needed. Work with software, validation and emulation teams as needed. Work on other aspects of verification like CDC, gate simulation. Work on lab bring up and silicon validation.


#LI-DNI


Education:
  • Bachelor’s degree or foreign equivalent in Electrical Engineering, Computer Science, or related field.
Experience:
  • 5 years of progressive experience as Verification Engineer, Member of Technical Staff, Senior Engineer, or related occupation.
Alternate Requirements:             
  • Will also accept a Master’s degree or foreign equivalent in Electrical Engineering, Computer Science, or related field and 3 years of progressive experience as Verification Engineer, Member of Technical Staff, Senior Engineer, or related occupation.
Special Requirements:
  • Must have at least 1 year of prior work experience in each of the following:
  1. Building test benches using UVM verification methodology and System Verilog;
  2. Writing functional coverage and SVA (System Verilog Assertions);
  3. Block level test bench development and silicon bring up and silicon validation;
  4. Create block level and Sub system level verification plan, test plans and full chip test plan and create tests and port block level tests to full chip test bench;
  5. Working with designers to obtain coverage closure;
  6. Integrating Verification IPs [VIPs] in the ASIC verification environment; and,
  7. Work with software, validation and emulation teams.
#LI-DNI


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