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Senior Packaging Design Engineer

155786
Hyderabad, India, India
Oct 16, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 

In this key technical position, you will leverage your package design expertise and engage in the following undertakings.
  • Designs advanced and heterogeneous integration packages for All Programmable devices to meet/exceed package and system electrical and thermal performances
  • Develops new package solutions including pin-out definitions, DRC/DFX and stack-up requirements
  • Develops design automation and methodologies
  • Implements chip-package design flow and LVS verification
  • Provides packaging expertise to support succeeding processes: manufacturing, assembly, testing, reliability and VNC
Job requirements
  • Expertise in CADENCE Allegro Package Designer, including constraints setup
  • Familiarity with Excel, AutoCAD, Gerber/ODB++/GDSII conversion software, and DFM tools
  • Skill programming experience is a plus
  • Experience in CADENCE Allegro Package SI, Allegro Sigrity or other SI tools is a plus
  • Knowledge in packaging substrate structures and manufacturing
  • Knowledge in 2.5D/3D, flipchip, WLP and wirebond assembly and reliability
  • Knowledge in SPICE, signal/power integrity, DDR3/4, and SerDes channel modeling for high speed design
  • Knowledge in stress and thermal modeling on microelectronics packaging
  • Good communication skills

 

Education Requirements
Bachelors with 4+ or Masters in EE or related fields
Years of Experience

a minimum of 5 years of relevant experience in advanced package design

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