DescriptionXilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
Xilinx is looking for an experienced and motivated leader to join the DataCenter
solutions, PCIe Connectivity, and Networking Acceleration engineering team.
As part of this team, you will play a key role in the design and implementation
of next generation FPGA-based intellectual property (IP) blocks for the cloud
scale-out data centers. IP includes Machine Learning, PCI Express, Multi-
Queue DMA, Networking Acceleration, and other protocols.
Come join us and be part of team that delivers world-class products that
set the industry standard for quality, ease of use and customer support. In
this role, you will have the opportunity to drive the design, verification, and
validation of FPGA hard IP blocks as well has companion soft solution IP block.
In addition you will work across the hardware/software boundary.
Education and Years of Experience Requirements: Minimum of a BS with 12+ years or MS with 8+ years or PhD with 5+ years
Education/Field Requirements: Electrical Engineering, Computer Engineering or related equivalent
- Knowledge in multi-queue DMA and Networking implementations is a plus
- Experience with planning, architecture, design, and implementation of complex IP
- Experience with Verilog required
- Experience with FPGA design a plus
- Knowledge of PCIe, AXI, Networking protocols a plus
- Ability to quickly analyze and debug RTL issues
- Excellent oral and written communication skills with ability to motivate, mentor and develop a world-class team