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Static Timing Analysis Engineer

155668
San Jose, CA, United States
Aug 9, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!


Static Timing Analysis Engineer

•The candidate will be responsible for completion of tasks that include timing closure and signal integrity.

•Develop and implement plans to close timing including Design-For-Test (DFT) on complex digital integrated circuits at the block level (100K to 1M+ gates) which are coded in VHDL/Verilog

•Design, implement Static Timing Analysis scripts using best-in-class methodologies

•Extensive experience in static timing analysis, power and noise analysis across multiple projects

•Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones

•Provide/propose new/enhance STA, synthesis and DFT flow and methodology

•Experience in Design-For-Test tools & methodologies (Scan chains, ATPG, BIST, Fault models, Fault Coverage and generation)

•Experience in Synopsys or Cadence timing and physical design tools

•Experience in interfacing with physical design teams

•Experience with Verilog/VHDL and Digital Design Principles

•Work with various design groups across different disciplines (Logic, Circuits & DFT) to meet timing closure, area, power, and performance requirements

•Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule

•Successfully track records of taping out complex SOC in 16nm and beyond

•Working knowledge of deep sub-micron power, SI and timing issues

•Strong scripting skills in Perl, TCL and Shell, particularly in synthesis & timing analysis

•Document all the STA deliverables

•Self-motivated team worker, good verbal and written communication skills

Education Requirements and Experience

BS degree in Engineering (e.g. Electrical, Mechanical, Industrial, etc) or equivalent practical experience. 
2+ years of experience in ASIC physical design flows and methodologies in 7nm, 16nm and 28nm process nodes. Multiple foundry experience. 
Experience in STA, synthesis, DFT, physical design, power analysis flows and methodologies using tools such as Design Compiler, ICC/ICC2, Innovus/EDI, Primetime, Spyglass and Power Artist. Experience with scripting in TCL, Perl, Python. Strong written, verbal and debugging skills. Knowledge of DRAM memory controller design and architecture is a plus
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