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Hardware Design Verification Engineer

155663
San Jose, CA, United States
Oct 10, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!


Xilinx is looking for a motivated DV engineer to join the DC solutions and PCIe Connectivity IP engineering team. As part of this team, you will play a key role in the design and verification the next generation FPGA-based intellectual property (IP) blocks for System Interconnect protocols such as PCI Express, Quick Path Interconnect and other similar protocols.

Come join us and be part of team that delivers world-class products that set the industry standard for quality, ease of use and customer support. In this role, you will be responsible for the design and verification of these interconnect protocol blocks. You will have the opportunity to be a key member of the implementation of FPGA hard IP blocks, as well has companion soft solution IP blocks such as DMA, AXI, Crypto and Machine Learning.

#sb


Qualifications:

·        Excellent ability to analyze and debug RTL design issues is required.

·        Functional coverage planning/development skills are required.

·        An object oriented programming language such as C++ or System Verilog are required.

·        Knowledge of serial protocols such as Ethernet, Infiniband, DMA, AXI, ML is a plus.

·        Expertise complex random-constraint verification methodology

·        UVM experience is a plus.

·        Verilog HDL is required.

·        Excellent oral and written communication skills with ability to motivate, mentor and develop a world-class team

Education:

·        BSEE with 3+ years or MSEE with 1+ years of relevant experience


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