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Design Engineer

155588
Singapore, Singapore, Singapore
Jul 17, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!


Design Engineer

The engineer will work as part of a cell library design team, in close collaboration with the design automation (CAD) teams to develop and enhance the development and regression platforms. The engineer’s main responsibilities are the design and development of advanced technology node standard cell libraries. These libraries contain both traditional and complex standard cells that significantly enhance implementation turnaround time while maintaining circuit performance with improved area/power trade-offs.

Cell based design/Place and Route methodology is playing a more significant role in our deep sub-micron designs, due to both design complexity and the challenges poised from the process technology.

In this highly visible role, the engineer will be working on multi disciplines, with a
critical impact on getting functional products to market quickly. The engineer is to be self-motivated to continuously develop skills and accept a variety of
responsibilities as part of contributing to the design center’s success. Also, the
engineer is to be able to communicate well and demonstrate a positive learning
attitude.

The Design Engineer will perform the following key responsibilities:
  • Responsible for developing optimal circuit solutions using advanced technology nodes that enable better design performance, with improved area/power trade-offs.  
  • Responsible for standard cells libraries development, including Virtuoso OA databases and cell modelling such as timing (liberty), functional (RTL/verilog) and power models (APL).
  • Responsible for developing and updating the standard cell design regression flows.
  • Engage with design and CAD teams to understand new library cells requirements for static timing, dynamic power, electromigration and place and route (PnR)/cell based design. 
  • Maintenance of the standard cell source database and regression platform.
  • Verification of functionality and performance of all deliverables.
  • Evaluate best in class EDA tools in the industry

    Education Requirements

    The successful incumbent should be/possess the following:
    • At least a Bachelor Degree in Electrical/Electronics/Computer Engineering
    • Solid understanding of MOSFET electrical characteristics and experience with transistor level circuit simulators, such as HSPICE and SPECTRE.
    • Understanding of layout at the transistor level in order to effectively work with the mask design team. Familiarity with reviewing DRC and LVS results is an added advantage.
    • Experience in and a good understanding of standard cell architectures, including state retaining elements like latches and flops.
    • Familiarity with working in the Linux environment, SKILL programming, load sharing concepts (such as LSF) and version control (such as ICManage) is a plus.
    • Having some PnR/semi custom background, especially in the chip level floorplanning is an added advantage.
    • Understanding of and an ability to learn a wide variety of industry standard modeling formats including Liberty (CCS, ECSM, and NLDM), Verilog, LEF, Milkyway, SPICE.
    • Able to work independently. 

    Years of Experience
    • Minimum 3 years relevant experiences.
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