Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
The Architecture group at Xilinx plays a pivotal role in development and analysis of next generation Xilinx ACAP devices. We are seeking passionate design engineers to join the team in Hyderabad, India.
This candidate will analyze and evaluate upcoming FPGA Architecture’s capability to meet market requirements as well as beat competition, generate insights for FPGA architecture’s and tool’s limits. The candidate will analyze performance, power, routability and resource requirements for key use cases in wired, wireless, automotive and other end market segments. The candidate will also make recommendations to FPGA designers, in terms of constraining or re-writing HDL in order to maximize performance on a given Architecture.
Typical responsibilities include
§ Digital logic design (Verilog/VHDL) to create/edit designs and implement them on FPGA tool suite (Vivado) both in evaluation and production flows
§ Assess performance/power/resource usage to compare against requirements, generate insights for Architecture and FPGA Synthesis, Place and Route tools from design analysis
§ Understand design trends in various end market use cases and propose FPGA feature enhancements
§ Implement challenging designs in FPGA tool flow in help achieve timing closure on new architectures
§ Find routability hot-spots, make constraint recommendations to relieve the same
§ Create designs to mimic routability challenges in key market segments
§ Master’s in EE/CE and 4+ yrs of experience or Bachelors with 6+ yrs of experience
§ Extensive experience in design implementation with FPGA tools
§ Basic understanding of FPGA Architectures and Tools (Place & route, synthesis, timing)
§ Verilog/VHDL and scripting languages (TCL, PERL or PYTHON)
§ Good oral and written communication skills are essential
§ Self-driven and motivated, able/willing to work with teams globally