Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).
As a member of the FPGA Silicon Design Full Chip RTL team, you'll be responsible for development of RTL models for synthesized and custom logic. Using formal verification tools to prove the RTL models are accurate to the transistor model. Use power models to describe the power intent of the model. Verify the clock domain crossings are correctly designed. Help develop and prove new RTL methodologies.
Responsibilities will include but are not limited to
Years of Experience
· Exceptionally strong System Verilog coding skills.
· Experience synthesizing RTL with Design compiler or Verific
· Experience running formal verification with Conformal or Formality.
· Experience in RTL functional simulation, Writing simple test benches, using Verdi to debug behavior.
· Nice to have : UPF power modeling, ESP verification, Verific coding skills.