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Senior Engineer RTL Design

155476
San Jose, CA, United States
Jul 13, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI). 


Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

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As a member of the FPGA Silicon Design Full Chip RTL team, you'll be responsible for development of RTL models for synthesized and custom logic. Using formal verification tools to prove the RTL models are accurate to the transistor model. Use power models to describe the power intent of the model. Verify the clock domain crossings are correctly designed. Help develop and prove new RTL methodologies.

 

Responsibilities will include but are not limited to

  • Exercises solid analytical problem solving and troubleshooting skills (e.g., LEC debugging, Functional simulation debugging, Script debugging )
  • Model the power profile of a design and use power reduction techniques on the design.
  • Run LEC on synthesized designs at several places in the design cycle, Pre DFT,Post DFT, Post Layout, ECO
  • Coordinate with tool vendors to resolve tool issues, make test cases to show issue.
  • Mentor less experienced design engineers in implementation tasks to ensure compliance to specification, quality standards, and milestones
  • Strong scripting and automation using Perl, Python, TCL, Make and/or other scripting languages

Education Requirements

  • Master’s degree in Electrical Engineering or related field. 

Years of Experience

  • 4 years of progressive experience as IC Design Engineer, CPU/ GPU/ FPGA Hardware Engineer, ASIC RTL Design  or related occupation 

Alternative Requirement:          

  • Bachelor’s degree in Electrical Engineering or related field plus six (6) years of progressive experience as IC  Design Engineer, CPU/ GPU/ FPGA Hardware Engineer, ASIC RTL Design or related occupation

Experience Required:   

·         Exceptionally strong System Verilog coding skills.

·         Experience synthesizing RTL with Design compiler or Verific

·         Experience running formal verification with Conformal or Formality.

·         Experience in RTL functional simulation, Writing simple test benches, using Verdi to debug behavior.

·         Nice to have : UPF power modeling, ESP verification, Verific coding skills. 

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