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Layout Design Engineer

155463
Hyderabad, India, India
Jun 15, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, programmable SoCs and the ACAP, designed to deliver the most dynamic processor technology in the industry and enable adaptable, intelligent computing.

If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for bold, collaborative and creative people to help deliver groundbreaking technologies that build an adaptable intelligent world. Come do your best work and live your best life through collaboration, wellness and giving back to your community as a member of the ONEXILINX team.


Shared

Design Flow and Tools
  • Good debugging skill of all the related tools and design flow setup.
  • Thorough understanding of FPGA integration, associated tools to generate the full-chip and verification flows.
  • Good understanding of physical verification languages like SVRF and SKILL.
Design Implementation and Verification
  • Should take responsibility of a complete block and deliver the quality layout to the next level integration.
  • Analyzes problems upfront, identifies gaps and provides optimum solution.
  • Assists other engineers in troubleshooting with his technical knowledge.
  • Takes the ownership of a large block level layout.
  • Good understanding of FPGA architecture and floor-plan.
  • Provides proper guidance to junior staff for block layouts and communicates the requirements well at all levels.
  • Good understanding of all the tape-out flows.
Design Requirements Assessment
  • Assesses proposed component features to help determine cost-effectiveness and feasibility
  • Provides input to system architects in shaping and formalizing component roadmaps, resource needs, and milestones
  • Can properly analyze how all the elements of a design solution fit together
  • Can perform an End to End System performance analysis
  • Can properly evaluate internal and 3rd party IP solutions against requirements
Master’s/Bachelor’s Degree in Electrical/Electronics engineering with a minimum of 5+ years of experience in Analog Mixed Signal Layout. Successful candidate would be responsible for layout in advanced CMOS technologies including floorplan, placement, routing, DRC, LVS etc. You should have worked on 16/14nm (7nm would be advantage) on various analog mixed signal blocks such as PLL, Bandgap, ADC, DAC, SERDES, IO etc. Engineer should be well versed with tools such as Virtuoso/XL/GXL, IC12.1, Calibre etc. You are required to work with circuit designers to meet design specifications. This job requires excellent teamwork, good communication and strong problem solving skill.
 
Job Requirements:
 
  • Responsible for independent planning and execution of layout for various designs in 16nm technology nodes and below.
  • Hands on experience in all stages of the design such as Floorplanning, Placement, Layout, Physical Verification etc.
  • Strong debug capabilities with parasitic extraction, LVS/DRC and other Physical verification checks.
  • Knowledge of scripting languages like SKILL, PERL, TCL etc. is desirable.
  • Strong problem solving skills.
  • Excellent communication skills.
  • Sound knowledge of device matching, pitch matching, double patterning and other Layout Dependent Effects.

Education Requirements

Master’s/Bachelor’s Degree in Electrical/Electronics engineering

Years of Experience

 

5+ years

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