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Staff STA Timing Design Engineer

155391
San Jose, CA, United States
Aug 9, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

 

This STA position is in the Serdes Technology Group for an experienced Engineer to focus on synthesis and STA for SerDes. A brief description is as follows.

 

The successful candidate will be responsible for Design Implementation (Synthesis/STA/Timing closure) SerDes. The role will include driving and optimizing synthesis, power optimization, static timing analysis, and logic verification using an industry leading ASIC design flow. It will require a proactive candidate with a proven record of success in cross functional and cross site team environment. The candidate is required to drive and enhance Synthesis, Static Timing and Power Optimization methodologies, for the STG  group.

 

 

 

  

• BSEE with 8+ years of experience or MSEE with 6+ years in ASIC implementation activities such as synthesis and STA.
•Top level and block level Synthesis and timing closure ownership high speed designs.
•Drive SoC timing budgets, develop timing constraints, power optimization, and timing closure sign-off activities.
•Work closely with digital, analog, and physical design teams to optimize for performance, power, and area.
•Drive low power implementation and optimization methodologies using UPF/CPF
•Drive Formal Verification (logic equivalency) flows for the designs Develop and maintain RTL-to-Netlist tool flows and methodologies.
•Good exposure to Synopsys tools such as design compiler, primetime and formality
•Good inter personal skills and able to interact well with other members in the functional teams of the business unit.
•Good communication skills.
Preferred Requirements:            
•Prefer 5-6 years of experience in ASIC implementation tasks.
•Participate in Library and Memory IP selection (bench-marking/evaluations), characterization, and configuration.
•Participate in SoC development planning and scheduling.
•Assist in the validation and debug silicon products in support of release to production.
•Experienced in automating flows. Good scripting skills (TCL/Perl/Python)
•Experienced in timing closure and sign-off activities with high speed IOs.
•Familiarity with physical design flows and assist the physical design team when required.
•Interact with tool vendors and debug tool related or IP related issues independently.
 
 
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