develops highly flexible and adaptive processing platforms that enable rapid
innovation across a variety of technologies - from the endpoint to the edge to
the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and
the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most
dynamic processor technology in the industry and enable the adaptable,
intelligent and connected world of the future in a multitude of markets
including Data Center (Compute, Storage and Networking); Wireless/5G and Wired
Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace &
Defense; Industrial Scientific & Medical, and others. Xilinx's core
strengths simultaneously address major industry trends including the explosion
of data, heterogeneous computing after Moore's Law, and the dawn of artificial
Our global team is growing and we are looking for bold, collaborative and
creative people to help us lead the industry transformation to build an
adaptable intelligent world. We believe that by embracing diverse ideas,
striving for excellence in all that we do, and working together as a unified
team, we can accomplish anything. Come do your best work and live your best
life as part of the ONEXILINX team!
We are looking for a talented, self-driven and motivated Staff SI/PI Engineer with a strong experience in simulation and verification to join the Board Development team in San Jose. You will be involved in the SI/PI simulations of high performance, complex boards for some of the most advanced applications in 5G Wireless/IoT/AI/Machine Learning. You will have an opportunity to work in a positive environment where individual development goals are aligned with organizational goals in developing products for some of the life changing and futuristic applications.
- Responsible for Signal Integrity and Power Integrity simulations at feasibility, pre-layout, post-layout phases of product design
Responsible for coordinating with HW design team, layout team, NPI and manufacturing vendors to resolve SI/PI related issues
Responsible for providing and maintaining PCB high speed layout guidelines
Responsible for reviewing PCB stackup, dielectric material, routing strategy and geometry definition.
Responsible for end-to-end channel simulations for multi gigabit SerDes channels, 28Gbps, 56Gbps and beyond.
Responsible for SI and timing margin simulations of HBM/DDR3/DDR4/LPDDR4 and other memory buses
Work with multiple teams distributed globally
Signal integrity support for hardware engineers during board bring-up and debug.
Responsible for characterizing the various interfaces in the product and correlation between the simulations and lab measurements.
Responsible for preparation of and implementing signal integrity checklists for various stages of development.
Years of Experience:
8+ years of relevant SI/PI simulation and characterization experience
Solid background on transmission line theory and in-depth knowledge of electromagnetics.
Excellent experience with Ansys HFSS, Cadence PowerDC, PowerSI and Agilent ADS.
Excellent experience in 100G Ethernet, QSFP28, PCIe Gen3/4, Multi Gigabit serial buses of 56Gbps and higher, DDR4/LPDDR4 etc.
Hands-on experience in electrical/design validation/compliance testing using high speed scopes, TDR, VNA and other instruments.
Excellent written and oral communication skills