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Staff SerDes Validation Engineer

155274
San Jose, CA, United States
Jul 12, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team! 

 

As a senior member of the SerDes System Engineering and Validation team, you will use your knowledge of high speed SerDes technology to lead validation efforts on Xilinx transceivers.
 
Responsibilities:
 
  • Define methodologies for validating high speed transceiver blocks
  • Ensure transceiver meets protocol compliance requirements for standards such as PCIe, OIF and 802.3
  • Work with customers to define system level tests and create demos
  • Work with Design and Architecture teams to correlate silicon performance with simulations
  • Develop FPGA test designs, firmware and software to validate transceivers
  • Review PCB design for high speed transceiver characterization boards
  • Mentor junior engineers on emerging methodologies and protocol standards 

 

 

Qualifications:
  • Bachelor's Degree in Electrical Engineering or Computer Science or related fields with 10+ years or MS in EE, CS or related fields with 8+ years of work experience with high speed transceiver testing
  • Hands on experience with test equipment such as scopes, BERTs and Analyzers
  • Experience with test and debug of PAM-4 links
  • Experience in Python/C++
  • Familiarity with FPGA design flow is a plus
  • Familiarity with SI analysis tools such as HFSS is a plus
  • Strong written and verbal skills
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