Xilinx is seeking an experienced front end implementation engineer for the development of high-performance IP blocks in the company’s next generation product. Successful candidates will be responsible for prototype implementation of assigned IP blocks to ensure RTL meets all defined quality metrics. As a member of the Processor Systems Design group, you will work on both design flow automation and product implementation for tapeout. Close interaction with both the RTL design team and signoff/backen-end implementation team is essential. Responsibilities include SDC generation/verification, logic synthesis, running RTL LINT, DFT DRC, and CDC verification. Additional responsibilities may include the development of power intent constraints (UPF), running LEC, Memory BIST insertion, and scan insertion. Maximizing efficiency through the effective use of automation throughout these processes is expected.
Applicants should possess a BS/MS in EE or equivalent field with applicable work experience in the several of the following tools. The position requires substantial TCL-based scripting competence within CAD tool shell environments as wells as stand-alone TCL shell scripts. Prior work experience in CAD, RTL, or front end implementation teams is expected.
Optional Experience (experience with 2 or more of the following is desired):
Experience and Education:
Highly motivated candidates with strong written and verbal communication skills and structured, well-organized work habits are desired.