develops highly flexible and adaptive processing platforms that enable rapid
innovation across a variety of technologies - from the endpoint to the edge to
the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and
the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most
dynamic processor technology in the industry and enable the adaptable,
intelligent and connected world of the future in a multitude of markets
including Data Center (Compute, Storage and Networking); Wireless/5G and Wired
Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace &
Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths
simultaneously address major industry trends including the explosion of data,
heterogeneous computing after Moore's Law, and the dawn of artificial
Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!
Xilinx, the world's leading company specialized in FPGA, is looking for some interns to work on C++-based high-level programming tools to ease FPGA programming with improved productivity. FPGA are reconfigurable MPSoC including CPU, GPU, reprogrammable logic and various specific accelerators (video CODEC) and I/O subsystems (100 GigE, PCIe, memory buses.). This complexity makes them versatile systems that can be used as accelerators but this also makes their use difficult compared to simpler CPU-only environments.
Fortunately, at the same time there are various open standards for heterogeneous computing, such as OpenCL or OpenMP 5, being developed to ease the programming of accelerators. Xilinx is pushing these standards as a way to simplify FPGA programming.
The Domain Specific Languages (DSL) are an interesting high-level approach to simplify programming by specializing on the problems to be solved. OpenCL SYCL is a DSL based on pure modern C++ to represent the concepts used to program accelerators directly as C++ class without any extension or compiler to avoid portability issues.
The goal of this internship is to develop a SYCL open source environment targeted FPGA and CPU for emulation:
- a first part is to extend the runtime implementation https://github.com/triSYCL/triSYCL based on OpenCL and OpenMP API;
- a second part is to improve the current triSYCL device compiler based on open-source compiler Clang/LLVM able to extract the code of the computational kernels and generate the SPIR 2.0 portable intermediate representation to address the existing Vivado HLS and SDx tools from Xilinx;
- improve the performance of triSYCL by collaborating with Vivado HLS & SDx teams;
- use & extend some applications such as the SYCL C++17 ParallelSTL or TensorFlow Eigen to extend triSYCL;
- in parallel to the implementation, a prospective research to define the standards themselves will be done.
The position is based in Dublin (Ireland) and will suit a Masters or PhD qualified student with a passion for C++ and OpenCL SYCL
The candidate will have the opportunity to get involved into advanced technologies through the standardization committees of Khronos OpenCL & SYCL, SPIR, Vulkan, OpenMP and C++, and meet all the leading companies and laboratories behind these technologies.
The areas and subjects of the internship are:
- implementing parallel languages and run-times (OpenCL SYCL 1.2.1 https://www.khronos.org/sycl and OpenMP 5 http://openmp.org);
- compilation (Clang/LLVM http://llvm.org/ and SPIR-V https://www.khronos.org/spir );
- FPGA & accelerators;
- C++17, STL, Boost;
- DSL & DSeL;
- HPC & real-time applications and libraries;
- open source software used for C++ development;