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Senior ASIC Design Engineer

154661
San Jose, CA, United States
Mar 27, 2018

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Job Description

Description


Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3DICs. Xilinx's all-programmable devices are designed into tens of thousands of products that improve the quality of the everyday lives of billions of people worldwide. For over 30 years, Xilinx has been behind some of the greatest advancements in technology and science - from the industry's first fabless semiconductor model to the NASA Curiosity Mars Rover, to today's autonomous vehicles and hyperscale data centers. Xilinx uniquely enables applications that are both software-defined, yet hardware optimized - enabling smart, connected and differentiated applications across technology's biggest megatrends, including Machine Learning, 5G Wireless, Embedded Vision, Industrial IoT and Cloud Computing and more. 

If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for bold, collaborative, and creative people to help deliver groundbreaking technologies that enable our customers to differentiate. Come do your best work and live your best life through collaboration, wellness and giving back to your community as a member of the ONEXILINX team.


Senior ASIC Design Engineer

Xilinx' design team seeks a candidate for design of a memory controller of latest cutting edge DDR technologies.

 

Responsibilities:

  • Writing documentation and specs
  • Writing RTL in Verilog
  • Interact with other engineering teams for physical design and software.
  • Contribute to methodology
  • responsible for all design analysis.for backend STA, CDC, Power. #ey

Qualifications:

  • Master's Degree in Electrical Engineering with 5 plus years experience or PhD Electrical Engineering with 2 plus years experience.
  • Demonstrated knowledge of DDR memory technology: DDR4/5. LPDDR3/4, HBM
  • Working knowledge of the definition of micro-architecture
  • Fluent with RTL Verilog and Hardware modeling
  • Ability to develop efficient, testable, scalable and well-documented RTL code
  • Experience with industry standard simulation, waveform debugging
  • Familiarity with synthesis, simulation, static timing, CDC-analysis
  • Understanding of logic low power design techniques and clock gating concepts
  • The individual should be knowledgeable of Verilog and SystemVerilog and familiar with scripting languages (Python, Perl) for automating solutions.
  • Good communication skills, self-motivation and teamwork are required 

 

 


 

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