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Senior Software Engineer - Architecture

154830
Hyderabad, India, India
Jul 27, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team! 


Hiring EDA professionals to shape the next generation of Xilinx FPGA Architecture. As part of Xilinx FPGA Architecture group, the person needs to muddle in broad range of problems in EDA and hardware domain. This position requires person to get an in-depth understanding of Xilinx FPGAs and work through placement, router algorithms to evaluate impact of proposed FPGA architecture features on PPA, routing congestion, runtime etc. The hire gets to solve problems bordering EDA and hardware domain.  

Mandatory Skills: 
C++ / C
Algorithms and data Structures
Experience in PnR or Synthesis or STA EDA tool development (FPGA / ASICs) 
Scripting preferably Python (or Perl) and tcl
Verilog / Vhdl coding
Timing concepts 

Preferred Skills:
Optimization
Timing analysis
Design debug (timing , QoR)
FPGA architecture #hot

Masters / Bachelors in EE /EC/CS with 8+ yrs of experience 


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