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Functional Verification Engineer

154827
San Jose, CA, United States
Mar 27, 2018

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Job Description

Description

Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3DICs. Xilinx’s all-programmable devices are designed into tens of thousands of products that improve the quality of the everyday lives of billions of people worldwide.  For over 30 years, Xilinx has been behind some of the greatest advancements in technology and science—from the industry’s first fabless semiconductor model to the NASA Curiosity Mars Rover, to today’s autonomous vehicles and hyperscale data centers.  Xilinx uniquely enables applications that are both software-defined, yet hardware optimized – enabling smart, connected and differentiated applications across technology’s biggest megatrends, including Machine Learning, 5G Wireless, Embedded Vision, Industrial IoT and Cloud Computing and more. 

 

If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for bold, collaborative, and creative people to help deliver groundbreaking technologies that enable our customers to differentiate. Come do your best work and live your best life through collaboration, wellness and giving back to your community as a member of the ONEXILINX team.


FDST Verification group is looking for a Senior Design Verification Engineer to provide technical leadership, contribution on FPGA  block, sub-system and full chip verification. The individual will help design, develop and use simulation and/or formal based verification environments, at block, sub system and full chip FPGA level, to prove the functional correctness of FPGA SoCs.

 

The ideal candidate is one who has a proven track record on driving strategies and successful verification execution on high performance IPs and/or SoC designs. Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the FPGA design teams with an eye towards improving overall product quality. #hot

 
Qualifications:
  • Bachelor's Degree w/ 5+ years or MS w/ 3+ years or PhD w/ 0 years in Electrical Engineering, Computer Engineering, or Computer Science.
  • Requires proven track record in technical leadership. This includes planning, execution, tracking, verification closure, and delivery to programs.
  • Requires strong experience with development of UVM, OVM, VMM and/or Verilog, SystemVerilog test benches for full chip testbench and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip FPGA fabric and SoCs.
  • Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification.
  • Verification experience in MathEngine/DSP optimized for wireless applications, AXI, NoC, HBM, DDR4, PCIe verification is a plus.
  • Verification experience in full chip verification is a plus.
  • Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
  • Strong understanding of different phases of ASIC and/or full custom chip development is required.
  • Experience in modeling SystemC and using SystemC based models in verification is a plus.
  • Experience with FPGA programming and software is a plus.
  • Verification experience in  PCIe, Processors, Graphics is a plus.
  • Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus.
  • Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
  • Some DFX/DFT and UPF/ power-ware - simulation experience is a plus
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