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Senior Verification Engineer

155118
San Jose, CA, United States
Jul 16, 2018

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Job Description

Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team! 

 

Xilinx FDST Verification group is looking for a Verification Engineer to verify high speed SerDes designs.
 
The individual will help design, develop and use simulation and verification environments, at block and full chip FPGA level, to prove the functional correctness of SerDes designs. Candidate is expected to be a strong team player with good communication skills and the motivation to excel.
 
The individual will have the following responsibilities:
  • Review design document and develop verification strategies for SerDes designs.
  • Develop verification plans and create block and chip level verification environments.
  • Create testcases to meet functional and code coverage goals
  • Debug failures in simulation and collaborate with designers in root-causing failures
  • Investigate methods to improve analog behavioral modeling for functional verification.


 

Qualifications:
  • Requires BS w/ 5+ yrs or MS 3+ yrs or PhD in Electrical Engineering, Computer Engineering or Computer Science.
  • Requires experience with testbench development using verilog, systemverilog and UVM, 
  • Requires good OOP programming skills in languages such as C++, Python, Java or Systemverilog.
  • Requires good understanding of logic design and digital circuit fundamentals.
  • Coursework with strong performance or experience with DSP and Communication Systems is a big plus.
  • Coursework or experience in analog and/or mixed signal circuit design.
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