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IC Layout Engineer- Contractor

154331
Singapore, Singapore, Singapore
Jun 21, 2019

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Job Description

Description


At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology.  We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice.  From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world’s first 5G networks, we empower the world’s builders and visionaries whose ideas solve every day problems and enhance people’s lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you!  At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – world class technology that improves the way we live and work.  We are ONEXILINX. 

The Serial Transceiver Group team designs high speed serial interface systems which are integrated into FPGA devices. These devices are used in a variety of applications such as automotive, wireline and wireless communications. Successful physical implementation of these serial communications solutions requires an advanced knowledge of mixed signal layout techniques.

 

Successful candidates will work as part of an experienced team executing projects in advanced CMOS manufacturing processes. Layout is extremely challenging at these smaller process nodes. Project tasks will include: layout of analog and digital circuits. There is the opportunity to contribute to methodology initiatives to accelerate design layout.

 

Job Description:

  • Design complex layout for mixed signal, and analog circuits. (including block level and chip level layout)
  • Review and analysing floor plans and complex circuits with circuit designer.
  • Run a complete set of design verifications.
  • Collaborate with the circuit design team to plan, and schedule work and negotiate any necessary layout tradeoffs as needed.
  • Utilize advanced CAD tools, mask design knowledge to layout correct and robust physical design representation of circuits.
  • Ability to work independently as well as in teams, including remote design teams

 



Qualifications:

  • BSEE preferred, at least three (3+) years of custom or analog IC physical design experience
  • Experience with schematic-driven layout, floor planning, chip level routing, design for manufacturing and design rule and connectivity verification is preferred
  • Understanding of cutting edge silicon process technologies (CMOS 28nm and below) and device physics
  • Hands-on experience using Cadence Virtuoso XL or GXL is preferred
  • Mentor Caliber experience to run DRC & LVS
  • Familiarity with analog and digital layout tools and flows, circuit design concepts and IC manufacturing processes
  • Understanding of parasitic impact on circuit performance is a plus.
  • Capable of top level floor planning with knowledge of transistor, resistor, and capacitor matching in sub-micron process.
  • Understanding of digital SOC flow is a plus.
  • Team player with good communication and documentation skills.
  • Capacity to take on board new approaches and working methods
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