This position is for MPSoC RTL design team in Hyderabad, which does significant part of Xilinx system-on-chip design that resides inside Xilinx FPGA devices. The requirement is based on new 7nm SoC development which uses the design flow using standard cell based design methodology. You'll be responsible for contributing for the frontend RTL design of complex subsystems. It involves taking design to micro-architecture and implementation from SOC Architecture specifications, owning, designing and driving subsystem IP design that includes microarchitecture, RTL design/Integration, design quality checks like lint, CDC, synthesis and static timing constraints development and validation.
During various design cycle you’ll be able to interact cross-functional teams thus leading and resolving design issues, achieving better subsystem performance, helping linux driver development issues related to design. The job will require experience in ARM based SoC’s and few core peripheral[as mentioned below] in a IO sub-system design and integrated silicon product development.
Essential Duties , Competencies & Responsibilities include, but not limited to:
- 10+ years of experience in SoC/IP RTL design/SoC Integration
- Expertise in Protocols like SD Host 3.0/4.0, Gigabit Ethernet, low speed peripherals(I2C, SPI, UART etc)
- Work experience in ARM CPU based SOC system is required
- Good AXI based system and AXI bus knowledge is must have
- Must have synthesis and STA constraints experience for at least 1 SoC
- Should have knowledge in clock domain crossing (CDC), Linting and fishtail constraint analyzer knowledge
- Team player with ability to work with multisite and local teams
- Should have ASIC/SOC design flow competency
- Should be able to own SoC level tasks for system/subsystem IPs
- Need Excellent communication skill and sound debugging skills
: BTec/MTech EE / EC from premier institutes.Years of Experience: 10+ years