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We are looking for a signal integrity engineer to design and analyze high speed interfaces and power distribution network. The candidate will work with other related design teams to define and design the product to meet power and high speed I/O requirements and help the lab measurement and debug.
Detailed responsibilities are listed below:
1) Power integrity analysis, which includes but not limited to layout extraction, HSPICE simulation to meet silicon noise spec and decoupling strategy and analysis.
2) Simultaneous switching noise/output (SSN or SSO) analysis for I/O power domain. Eye diagram and jitter analysis via Chip-package-board co-simulation.
3) Optimal layer stackup & VDD/VSS plane/island assignment to minimize voltage drop/noise/coupling.
4) Special noise-sensitive power supply analysis and layout guideline.
5) Signal trace length variation/matching and impact to timing.
6) Crosstalk analysis and reduction.
7) Insertion loss and return loss modeling and improvement with HFSS. #hot
The successful incumbent should be/possess the following attributes:
- Master of Science degree in Electrical & Electronics Engineering with 3-5+ years experience or PhD
- Solid background on transmission line theory and in depth knowledge of electromagnetics.
- Experience with HSPICE, HFSS, Q3D, PowerSI, and Agilent ADS.
- Experience with lab measurements using oscilloscopes, TDRs, VNAs, and spectrum analyzers.
- Self motivated, teamwork, and good communication skills.