Staff Software Engineer - EDA Software Architecture

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Software Engineering
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153756 Requisition #
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Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today's most advanced electronics. Among the broad range of end markets we serve are:

  • Aerospace/Defense
  • Automotive
  • Broadcast
  • Consumer
  • High Performance Computing
  • Industrial / Scientific / Medical (ISM)
  • Wired
  • Wireless

 

 

Staff Software Engineer
We are seeking a talented, self-driven and motivated software engineer to be part of the Xilinx Software Architecture team (SWAT). The SWAT team develops core software infra-structure for Xilinx applications. Being a member of the SWAT requires the passion and motivation to solve challenging technical problems with robust algorithms and features. Our code is optimized for high performance on large data sets and leverages leading edge industry standard technologies such as C++, STL, BOOST, Tcl, and more.
 
In this key technical position within the SWAT, you will leverage your EDA expertise to develop and maintain the core netlist and constraint infrastructure for Vivado Design Suite.
 
  • Analyzes the architecture and design of netlist/constraint infrastructure to support new FPGA devices.
  • Applies software architecture skills to improve the runtime and memory footprint of the netlist/constraint infrastructure.
  • Uses his/her EDA knowledge to ensure that the infrastructure supports Xilinx EDA tools like synthesis, placer and router.
  • Enables runtime efficient import and export operations on the netlist/constraint database.
  • Applies excellent written, verbal and interpersonal communication skills to work closely with the R&D, application and marketing teams.
  • Uses strong analytical and troubleshooting skills along with the EDA flow knowledge to enhance and maintain the netlist/constraint infrastructure. 

 

 

 

 

 

Qualifications:
  • 5+ years of software development experience in the EDA domain.
  • Expert in C++ programming.
  • Must be able to demonstrate strong analytical and problem solving ability.
  • Must be able to excel in a team environment with good interpersonal and communication skills.
 
Nice to have skills:
  • Familiar with FPGA EDA flow
  • Familiar with netlist and constraint infrastructures.
  • Worked on VHDL/Verilog/EDIF netlist import and export.
  • Familiar with scripting languages (TCL, Perl, Python, etc.)
Education:
  • Bachelors in EE/CS +9 years, or Masters in EE/CS +5 years or PhD in EE/CS +3 years relevant industry experience.

 


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