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Design Engineering
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153734 Requisition #
Thanks for your interest in the Senior Design Engineer position. Unfortunately this position has been closed but you can search our 219 open jobs by clicking here.
 
 
Special Requirements:        Must have at least 1 year of prior work experience in the following:
  1. Development of verification testbench components or environments using methodologies such as UVM, OVM or VMM
  2. Testplan development and testplan execution (test writing)
  3. Analyzing and debugging the failures in simulation using tools like Synopsys VCS, Cadence IES or Mentor Modelsim/Questa
  4. Coverage writing (including coverpoints, crosses), coverage collection and improving coverage of the design under test
  5. Writing assertions in system Verilog and performing assertion based verification
  6. Automation using scripting languages (Python or Perl)
     
    Education Required:           Bachelor or foreign equivalent in Electronics Engineering, Electrical Engineering, Computer Engineering, Computer Science or related field.
     
    Experience Required:         5 years progressive experience as Design Verification Engineer or related occupation.
     
    Alternate Requirements:    Will also accept Master’s degree or foreign equivalent in Electronics Engineering, Electrical Engineering, Computer Engineering, Computer Science or related field plus 3 years of experience in Design Verification Engineer or related occupation.

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